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(R)
ISO-CMOS ST-BUSTM FAMILY MT8950 Data Codec
Features
* * * * * * * Transparent coding and decoding of 0 to 8, 9.6 and 19.2 kbps data Coding compatible to PCM voice channels at 56/64 kbps in ST-BUS format Automatic line polarity detection and correction Loopback facility for test purposes Selectable data formats: RZ or NRZ Eight user selectable modes of operation Low power ISO-CMOS technology
ISSUE 4
November 1990
Ordering Information MT8950AC 24 Pin Ceramic DIP 0C to 70C
Description
The MT8950 is a coder/decoder which uses the Transition Encoded Modulation (TEM) technique for encoding/decoding low speed data to and from a 56/ 64 kbps channel (equivalent to PCM Voice). The coding and decoding scheme is transparent and can accept either synchronous or asynchronous data up to 8 kbps (inclusive); at 9.6 kbps and 19.2 kbps. The MT8950 is fabricated in MITEL's ISO-CMOS technology.
Applications
* * * * Transparent coder/decoder for synchronous and asynchronous data Data terminal (RS-232C, etc.) to ST-BUS interface Data switching on digital PBXs Channel banks/TDM multiplexers
DP SCLK DR 1 DR 2 DF DX 1 DX 2 RxE NRZ/RZ Input Circuit NRZ/RZ Output Circuit Timing & Mode Control Encoder Enable Logic
C2i F1i CA Decoder
DSTi ST-BUS Interface DSTo CSTi
Control Register DA Monitoring Interface SPo
NRZo SPi
PRST
VDD
VSS
Figure 1 - Functional Block Diagram
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MT8950
ISO-CMOS
CSTi DSTi C2i DSTo F1i CA DF RxE DX1 DX2 NRZo VSS
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VDD NC PRST NC NC DR1 DR2 DA SPo SPi DP SCLK
Figure 2 - Pin Connections
Pin Description
Pin # 1 Name CSTi Description Control ST-BUS In (TTL Input) - This ST-BUS interface pin accepts a serial input stream which loads the Control Register. The mode of operation of the device, the bits in the Violation word, and, the resetting of Data Activity (DA) and Scan Point output (SPo) are controlled by this register. The contents of the register are updated once every ST-BUS frame when the interface is enabled. Data ST-BUS In (TTL Input) - Accepts the 8 bits of TEM Data when the ST-BUS interface is enabled. 2.048 MHz Clock (TTL Input) - This is the input for the 2.048 MHz clock. ST-BUS Output (Three-State Output) - This is the 2.048 Mbps serial output for theTEM encoded word. It is enabled when both F1i and CA are low. Framing Type 1 Input (TTL Input) - This active low input, in conjunction with CA, enables the ST-BUS interface (DSTi, DSTo and CSTi). It is internally sampled on every positive edge of the C2i clock and provides frame synchronization. Control Address (TTL Input) - This active low input (in conjunction with F1i) enables the ST-BUS interface. Data Format Select (CMOS Input) - When HIGH, the Data Codec accepts and delivers the data in unipolar Return to Zero (RZ) format. When LOW, the data format is unipolar NRZ. Received Energy Signal (Schmitt Input) - When RxE goes LOW it establishes the polarity of the input pins DX1 and DX2 in the RZ mode. The input which received the last pulse before RxE goes LOW is established as the unipolar MARK input. RxE also enables the operation of DA and SPo outputs the loopback modes (Modes 4, 5 and 6) of the codec, RxE is forced to the LOW state internally independent of the pin condition. RxE should be exerted LOW for the duration of a data call. Data Transmit 1 (Schmitt Input) - If DF= LOW, accepts data in the NRZ format. (HIGH = MARK, LOW = SPACE). If DF=HIGH, accepts active low unipolar pulses representing the digital data in the RZ format. MARK or SPACE polarity is established by the RxE input.
2 3 4 5
DSTi C2i DSTo F1i
6 7
CA DF
8
RxE
9
DX 1
6-4
ISO-CMOS
Pin Description (continued)
Pin # 10 Name DX 2 Description
MT8950
Data Transmit 2 (Schmitt Input) - If DF = LOW, accepts data pulses which are encoded only if there is no activity on the DX1 pin - the data format and restrictions on the use of this input is explained in the text. If DF= HIGH, accepts active low unipolar pulses representing the digital data in the RZ format. MARK or SPACE polarity is established by the RxE input. Non-Return to Zero Output (Open Drain Output) - The incoming data, in the RZ format or the NRZ format , is internally converted to inverted NRZ and appears on this open drain output. This output in conjunction with the SPi input can be used for long space detection. Ground (0 Volt). Secondary Clock (TTL Input) - This is an external clock input that determines the timing of the Violation Word and the synchronization pulses. If these features are not to be utilized, this input can be tied to VSS. Drive Point Output (Totem-pole Output) - This output is exerted high when the Control Register bits b7, b6 and b5 are set to 110 (decimal 6). The operation of the Codec is normal in every other respect. Uncommitted Scan Point Input (Voltage Comparator Input ) - A LOW to HIGH transition on this input causes SPo to be set LOW. This is used to detect a long SPACE condition in conjunction with NRZo (pin 11). Uncommitted Scan Point Output (Totem-pole Output ) - This output is set LOW when the SPi input undergoes a LOW to HIGH transition. The SPo is reset by the presence of a logic "1" in bit b0 of Control Register. This function is active at all times except when RxE is false and during power reset conditions. Data Activity (Totem-pole Output ) - The NRZ/RZ input circuitry monitors the input signal (after polarity is established) and activates this output when it detects a SPACE on the input. This output is reset by the presence of a logic "1" in bit 1 of the Control Register. The DA function is active at all times except when RxE is false and during power reset conditions. Data Receive 2 (Totem-pole Output) - If DF = LOW ( NRZ format), outputs the secondary data signal in the NRZ form as explained in the text. If DF = HIGH (RZ format), outputs unipolar, active high MARK pulses. Data Receive 1 (Totem-pole Output) - If DF = LOW (NRZ format) , outputs the NRZ data signal. ( HIGH = MARK, LOW = SPACE) If DF = HIGH (RZ format), outputs unipolar, active low SPACE pulses. No connection. No connection. Power Reset (CMOS Schmitt Input ) - A LOW level on this input evokes the power reset condition for the codec. No connection. Positive Supply Voltage +5 volts 10% .
11
NRZo
12 13
VSS SCLK
14
DP
15
SPi
16
SPo
17
DA
18
D R2
19
D R1
20 21 22 23 24
NC NC PRST NC VDD
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MT8950
ISO-CMOS
Data Rate Bits/Sec Asynchronous Restrictions Synchronous Restrictions Percentage Distortion 0 - 8000 None None 3.2 9600 None None 3.8 19200 Minimum 2 Stop Bits None 7.5
Theory of Operation
The MT8950 is an encoder/decoder which operates on low baud rate data (up to 19.2 kbps) to convert it to the ST-BUS format. The data can subsequently be transparently switched or transmitted in a manner identical to PCM encoded voice. In this respect, the functional characteristics of the device are very similar to many industry standard voice codecs. Asynchronous and synchronous data from 0 to 8 kbps and at 9.6 kbps is accepted by the codec without any restrictions. Asynchronous data at 19.2 kbps should have at least two stop bits for the device to encode it properly. The data is encoded by the Codec into an eight bit word which occupies one 64 kbps channel on the ST-BUS. Conversely, it accepts an encoded 8 bit word from an incoming ST-BUS stream and regenerates the original digital signal. Mitel's ST-BUS is a synchronous time division multiplexed serial stream with a bit rate of 2048 kbps. In a telecommunications environment, it is generally divided into 32 channels made up of 8 bits each, with an effective bandwidth of 64 kbps per channel. These channels may carry data or PCM encoded voice. Low Speed Data Format The Data Codec can accept low speed data in either Non Return to Zero (NRZ) or Return to Zero (RZ) format. The NRZ format requires only one line to carry the data. This format is suitable for interfacing the data codec with RS-232 type terminals and microprocessor peripherals such as UARTS, ACIAs, etc. All signals have to be converted to TTL voltage levels before being input to the codec. The RZ format requires two separate lines to represent the MARKs and SPACEs in the data as illustrated in Figure 4. This format is useful when the data terminal is located some distance from the codec and the data is to be transmitted over a line as a three level signal (a positive pulse for the beginning of MARKs, negative pulse for the beginning of SPACEs and zero level for no change in the signal). The three level signal is converted to its TTL-Compatible binary form as shown in Figure 4 before being applied to the codec. A pulse appears on one line of the input indicating the beginning of MARKs. This is followed by a pulse on the second line indicating the beginning of SPACEs. If two or more pulses appear consecutively on the same line before the second line of the pair receives or transmits another pulse, then these pulses can be considered to be violating the normal rule of the RZ format and are called "Violation Pulses". The data codec will accept these violations with the restriction that the time difference between a violation pulse
Table 1. Summary of Data Codec Capabilities.
Refers to the maximum distortion in the bit period timing of the regenerated data. (Channel Bandwidth = 64kbps ) Percentage Distortion = |TBO - T BR | where
/ TBO
X 100
TBO = Original Data Bit Period TBR = Regenerated Data Bit Period
and an actual data transition be at least 125s. The violation pulses can be on the MARK or SPACE line. In a communications system, these violations can be used to carry other information when no data is being transmitted. Encoding/Decoding Scheme The Data Codec uses a Transition Encoded Modulation (TEM) technique to encode low speed data onto a 56 or 64 kbps equivalent PCM voice channel. This coding algorithm significantly reduces data bit distortion. The timing distortion in the regenerated data is summarized in Table 1. A simple sampling method for encoding the data would require a 256 kbps channel to obtain the same low distortion figures. If the encoded information is to be transmitted over digital T1/DS1 trunks, the maximum percentage distortion in the regenerated data is effectively doubled. This is due to the fact that the least significant bit in specific channels on these trunks is used to transmit signalling information. Thus the bandwidth per channel is reduced to 56 kbps. The encoder stage of the Data Codec observes data transitions in discrete timing windows which are 125s wide. These timing frames are further divided into 32 timeslots of 3.906s duration each (see Figure 3). The position of the first data transition, the total number of transitions, and, the time period between the transitions in this 125s frame is encoded as an 8 bit word. The first five bits (b0 to b4) indicate the position of the first data transition with respect to the 32 timeslots in the window. Bit 7 in the encoded word represents the absolute value of the data in the 31st timeslot. Bits 5 and 6 in conjunction with bit 7 are used to identify the total number of transitions and the time period between the transitions. Due to the fixed bit rate restrictions above 8 kbps, a maximum
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ISO-CMOS
MT8950
125 s Internal Clock 0 b7-1 # 1 1 2 1 3 1 4 b4b3b2b1b0 1 5 1 6 1 7 b1b0 b4b3b2b1b0 b4b3b2 1 0 0 1 1 1 0 b4b3b2b1b0 0 b4b3b2b1b0 1 b4b3b2b1b0=11111 1 2 3 4 5 6 7 8 9 10 *** 22 23 24 25 26 27 28 29 30 31 0 b70 1 1 Frame Type b6 1 1 b5 1 1
b4b3b2b1b0
0
1 1
1 0
0
1
0
1
2
3
4
0
1
2
3
4
5
6
7
Figure 3 - TEM Coding Scheme
(Note: Waveforms shown are bipolar RZ equivalent of separate RZ/NRZ inputs)
# 1 2 3 4 5 6 7
Frame Description No Pulse 2 Data Pulses (T=52 s) 3 Data Pulses (T=52 s) 1 Data Pulse Violation Pulse 2 Data Pulses (T=104 s) (Timeslot 4 to 31) 2 Data Pulses (T=104 s) (Timeslot 0 to 3)
Level b7 1/0 1/0 1/0 1/0 1/0 1/0 1/0
Frame Type b6 b5 1 1 1 1 1 0 0 1 1 1 0 0 1 0
First Transition b4 b3 b2 b1 b0 11111 XXXXX X X X XX XXXXX XXXXX XXXXX YYYXX
Notes
X X X X X 10001 (17) X X X X X 00100 (4) X X X X X = 0 to 31 X X X X X = 0 to 31 X X X X X > 00011 (3) XX = 0 to 3 YYY = 0 to 7
Table 2. TEM Coding Summary
Note: The Level bit (b7) indicates the level (HIGH or LOW) of the input data in timeslot 31 of the current frame.
of seven frames types are possible as shown in Figure 3. In frame type 7, the first five bits (b0 to b4) are used to represent two transitions instead of the normal first transition. Note that the data transitions in Figure 3 are shown as a three level signal. A positive transition indicates the beginning of one or more continuous MARKs and a negative transition indicates the beginning of one or more continuous SPACEs.
The decoder stage regenerates the original data from the 8 bit TEM word. The absolute values of the data signal in the present and previous frames as given by b7(n) and b7(n-1) are EX-ORed and the result in combination with the remaining bits of the TEM word is used to reproduce the original data with an accuracy of 3.906s (see Table 2). Due to the data speed restriction above 8 kbps, the second and third transitions (if any) will be reproduced at
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MT8950
ISO-CMOS
encoded as a single transition. The minimum time period between consecutive pulses should be 125s. The encoding of the NRZ/RZ data to the TEM format is performed by the encoder. The 8 bit TEM words are transmitted on the outgoing ST-BUS channel via DSTo. This is a three state output which is enabled only when both CA and F1i are low (see Figure 11). Receive Path The 8 bit word generated by a data codec at a remote end is shifted in from the incoming ST-BUS stream via the DSTi input. The word is shifted in at the same time as the outgoing word is shifted out, i.e., when both CA and F1i are low as illustrated in Figure 11. The NRZ/RZ low speed data is regenerated by the decoder section and output via D R1 and D R2. If the chip is operating in the RZ format, D R2 transmits MARK pulses and DR1 transmits SPACE pulses. The format of the output signal is shown in Figure 4. The width of an output pulse is nominally 35s and cannot be altered by the user. Violation pulses will appear on the line on which they were initially inserted at the remote end. In the NRZ format D R1 outputs the data. The second output pin D R2, transmits the secondary signal. Each transition in this signal represents one data pulse encoded by the remote end. An example of the type of waveform observed is illustrated in Figure 5. The NRZ/RZ output circuitry also transmits synchronizing pulses if the data decoded from DSTi is idling (i.e., no data transitions) for more than six clock periods of the Secondary Clock (SCLK). This Secondary Clock is typically a 600Hz input to the chip. When the codec is set in the RZ format, these sync pulses will be either MARK or SPACE violation pulses, depending on the last data bit transmitted. If it is operating in the NRZ format, the sync pulses constitutes a squarewave with high and low durations of six SCLK periods. This squarewave appears at the D R2 output pin. Synchronization pulses are transmitted until some activity is detected by the decoder or the mode of operation is changed through the Control Register. Timing Requirements The data codec derives all the internal timing from the 2.048 MHz clock input (C2i) and the two enable signals F1i and CA. The DSTo output goes from high impedance to the value of bit 7 of the TEM
intervals which are multiples of 52s (depending upon the input data baud rate).
Functional Description
The functional block diagram of the data codec is shown in Figure 1. The low speed data to be encoded is accepted by the NRZ/RZ input circuitry and relayed to the encoder. The 8 bit encoded word is transmitted within one channel time period on to the ST-BUS serial output stream. At the same time an 8 bit TEM word is loaded into the decoder via the incoming ST-BUS stream. The low speed data is regenerated and output by the NRZ/RZ output circuitry. The data codec can operate in eight modes. The specific mode of operation is selected by programming the internal Control Register using the CSTi serial input. Transmit Path The NRZ/RZ input circuitry can be programmed to accept RZ or NRZ data by asserting the appropriate level on the DF pin (HIGH=RZ format; LOW=NRZ format). In the RZ format, both D X1 and DX2 are used for the input data. MARK pulses are received on one line input and SPACE pulses on the other. The MARK and SPACE polarities of the input pins are fixed by the high to low transition of the RxE line. The input having the last transition before RxE goes low is selected to be the MARK input. Thus to ensure correct polarity selection, the data codec should be receiving MARK pulses before RxE is taken low. The RxE line must be kept low for the duration of the call. As indicated before, the Data Codec does accept violation pulses. The violation pulses can be input on the MARK or SPACE lines. The time difference between a violation pulse and an actual data pulse must be at least 125s. Since only one violation pulse is encoded per frame, the minimum time period between consecutive pulses should be 125s as illustrated in Figure 4. In the NRZ format, only one line is required for the data. This is input at DX1 (Pin 9). The second input, DX2, can be used for transmitting secondary control information. The signal on this input pin is encoded only when there is no activity on the D X1 line, i.e., during steady MARK or SPACE condition on the data line. To ensure proper encoder function, the signal to the D X2 line should be applied after at least 125s have elapsed since the last data transition on D X1. The acceptable data format for the DX2 input is illustrated in Figure 5. Each pulse on the line is
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ISO-CMOS
MARK D Bipolar RZ Equivalent D RxE D V V MARK D
MT8950
NRZ Equivalent
SPACE
SPACE
Establishes MARK polarity. See text for complete explanation. 52 s. Nom. or 104 s. Nom. or > 125 s
DX1 Input MARK Pulses (Polarity Established)
D
D
4 s. Min. Tb Max.
Tb = Bit Period 125 s. Min.
DX2 Input SPACE Pulses. D Signal Regenerated at Remote End D DR2 Output MARK Pulses 52 s. Nom. or 104 s. Nom. or > 125 s DR1 Output SPACE Pulses V = Violations Pulse; D = Data Pulse D D 35 s. Nom. D V 125 s. Min. V
125 s. Min.
35 s. Nom. D V V
Figure 4 - Example Input/Output Waveform in the RZ format (DF=HIGH) word on the first rising edge of the clock after F1i and CA are taken low. The 8 bit TEM word from the input ST-BUS stream is clocked into the device on the negative edge of the C2i clock. For proper codec operation, the ST-BUS interface (DSTo, DSTi,
52 s. Nom. or 104 s. Nom. or > 125 s DX 1 NRZ Input SPACE MARK SPACE 125 s. Min. DX 2 Secondary Input Signal Regenerated at Remote End DR1 Data Output DR 2 Secondary Output Each transition on this output denotes a pulse input at DX2 on the remote end SPACE MARK SPACE 125 s. Min. MARK 4 s. Min. 121 s. Max.
and CSTi) should be enabled for only 8 clock periods of the C2i clock in any 125s period (one ST-BUS frame time) as shown in Figure 11. All data input and output at the ST-BUS interface takes place at 2.048 Mbps.
MARK
Figure 5 - Example Input/Output Waveform in the NRZ format (DF=LOW)
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MT8950
ISO-CMOS
represented by a time interval of one SCLK period between the pulses. A logic "1" is represented by two clock periods. In the NRZ mode, the time interval between consecutive transitions of the signal carries the information. The modulation scheme is illustrated in Figure 6. The 8 bit word consists of a Control Register Bits b7 0 0 0 0 1 1 1 1 b6 0 0 1 1 0 0 1 1 b5 0 1 0 1 0 1 0 1 Normal Local Carrier Local Synchronization Digital Loopback Data Loopback Data Loopback - Local Violation Word Normal Mode - Drive Point Set HIGH. Idle
The Secondary Clock input (SCLK) is normally a 600Hz clock signal. This clock is internally aligned with the 2.048 MHz input. It is used to generate the synchronizing pulses and the violation word timing (when the chip is operating in the local carrier mode). Note that the 600Hz frequency is an exact multiple of the most commonly used baud rates, i.e., 300, 2400, 4800, 9600, and 19200. In synchronous data transmission schemes, the receiver timing circuitry can be kept in sync using the synchronizing pulses or the violation word when no data is being transmitted. Other clock frequencies can be used for specific applications. If this facility is not to be utilized, the SCLK input can be tied to ground. Control Interface An 8 bit word is read into the Control Register via the CSTi input at the same time as the TEM word is being shifted in. The chip functions controlled by the eight bits are summarized in Table 3 and described in subsequent sections. Bit 7,6,5 4,3,2 1 0 Function Device mode control bits. These bits select one of eight modes of operation Violation word control bits Resets the Data Activity Scan point Resets the Uncommitted Scan point
Mode of Operation
Table 4. Modes of Operation sync bit followed by seven other bits. Bits 1, 4 and 5 in this word reflect the values of bits 2, 3 and 4 in the Control Register. The remaining four bits in the word are fixed as zeros. The sync bit is identified by a time interval equal to four clock periods of SCLK. The NRZ/RZ input circuitry and the encoder stage operates normally in this mode. Mode 2: Local Synchronization. In the local sync mode, the NRZ/RZ output circuitry transmits only sync pulses on D R2. These sync pulses appear as MARK violations in the RZ mode with the time interval between consecutive pulses equal to four SCLK periods. In the NRZ format D R2 outputs a squarewave with a period equal to eight cycles of SCLK. D R1 output is held at steady MARK. The NRZ/RZ input circuitry and the encoder stage of the chip function normally. Mode 3: Digital Loopback. In this mode an 8 bit word from the incoming ST-BUS (DSTi) is sampled and one ST-BUS frame later, the same word is looped back to the corresponding outgoing channel of the ST-BUS (DSTo). This allows the user to test the ST-BUS transmission path to and from the data codec. Mode 4: Data Loopback. This mode permits the user to test the decoding and encoding operation of the codec. A known TEM word is sent to the data codec from the ST-BUS end. This word is decoded and redirected via the output circuitry to the NRZ/RZ input circuit and subsequently to the encoder stage
Table 3. Summary of Control Register Function Modes of Operation As mentioned earlier, the data codec can operate in eight different modes. The specific mode is selected through bits 7, 6 and 5 in the Control Register. Table 4 summarizes the different modes. Mode 0: Normal. This is the normal transparent conversion mode of the data codec. The NRZ/RZ input signal is directly encoded into the TEM format and output as an ST-BUS channel. The TEM word for the input ST-BUS channel is decoded and the regenerated data is output via the NRZ/RZ output circuitry. Synchronizing pulses are also transmitted as explained in the preceding paragraphs. Mode 1: Local Carrier. In this mode the NRZ/RZ output circuitry transmits an 8 bit word at DR2 (Pin 18) by modulating the secondary clock (SCLK). If the chip has been selected to operate in the RZ format, this word is transmitted as MARK Violations. The time interval between consecutive pulses specifies the binary value. A logical zero is
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ISO-CMOS
for transmission out on the ST-BUS output pin (DSTo). The NRZ/RZ inputs (Pins 9 and 10) are functionally disconnected from the input circuitry. The outputs (pins 18 and 19) are in a non-active state, i.e., D R1 is steady LOW and D R2 is steady HIGH. Mode 5: Data Loopback - Local Violation Word. This mode can be used for testing the operation of the chip in the local carrier mode. The Violation word is generated as in the local carrier mode. However, the modulated signal is not output on DR2. It is rerouted to the NRZ/RZ input circuit, encoded into the TEM format and output on DSTo. Mode 6: Normal Mode - Drive Point Activated. The drive point output (Pin 14) is set HIGH in this mode. The codec operation is normal in every other respect. This drive point can be used to control external circuitry. It is reset when the mode of operation is changed. Mode 7: Idle. In the idle mode D R1 and DR2 outputs are in a non-active state, i.e., D R1 is steady LOW and DR2 is steady HIGH. The encoder stage and the input circuitry operates normally. Device Monitoring Features There are two output pins which can be used to monitor the codec.
MT8950
1. Data Activity (DA): This output goes from high to low when a SPACE signal, indicating the beginning of data activity, is received by the NRZ/ RZ input circuitry. The level on this pin is reset by setting bit 1 of the Control Register to logic "1". 2. Scan Point output (SPo): This output is set LOW whenever SPi input undergoes a low to high transition. It is reset by a logic "1" in bit 0 of the Control Register. The SPi input is generally used in conjunction with pin 11 to detect a long SPACE condition in the data. The external circuitry required to utilize this feature is illustrated in Figure 7. Note that Pin 11 (NRZo) is an open drain output. The NRZ/RZ data input to the codec is converted to the NRZ format and output on this pin. The RC time constant for the circuit shown in Figure 7 can be set to detect SPACE conditions of varying time durations. The length of the long SPACE detected is given by TSP=0.7RC Where TSP is the duration of the SPACE in milliseconds. A long SPACE of 150ms is generated when the BREAK key on a data terminal is depressed. To detect this signal, a value of R equal to 210 k and C equal to 1.0F can be used.
CRB = Control Register Bit
SYNCH
b0
b1 CRB2
b2 b3
b4 CRB3
b5 CRB4
b6
SYNCH
b0
b1 CRB2
b2 b3
b4 CRB3
b5 CRB4
b6
35 s Nominal
DR 2 Output (RZ Mode) SYNCH 6.7 0.83 msec
b0 1.67 msec
b1 0=1.67 msec 1=3.33 msec CRB2
b2 1.67 msec
b3 1.67 msec
b4 0=1.67 msec 1=3.33 msec CRB3
b5 0=1.67 msec 1=3.33 msec CRB4
b6 SYNCH 1.67 msec
DR2 Output (NRZ Mode)
Note: The polarity of this output can be inverted - depending on the state of the last transition.
Figure 6 - Violation Word Timing in the Local Carrier Mode for a 600Hz input to SCLK
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ISO-CMOS
1. 2. 3. 4. 5. 6. 7. DSTo SPo DA DP DR 1 DR 2 NRZo High Impedance +5V (unasserted) +5V (unasserted) GND (unasserted) +5V (inactive) GND (inactive) GND (Mark condition)
The SPo pin could then be monitored by the system processor to detect a prompt from the peripheral.
MT8950 +5V R 11 C NRZo 16 SPo 15 SPi
The FF.
internal Control Register is loaded with HEX
Applications
Figure 7 - Long Space Detection Circuit External Power Reset When the reset input (PRST) is taken low, the data codec circuit goes into reset mode. The conditions present on the output pins are as follows: A block diagram schematic of a simple Voice-Data integrated switching system is illustrated in Figure 8. The data terminal can access a number of remote devices via the gateway provided by the Data Codec. In this application, the Data Codec function parallels that of the Voice Codec, i.e., the Voice
Digital PBX Data Codec Voice Codec ST-BUS Format Voice Codecs Main Frame Computer Data Codecs
Data Terminal Equipment
T1/CEPT Interface
MT8980 Digital Switch
MPU
ST-BUS Format T1/CEPT Leased Lines 1.544 Mbit/s or 2.048 Mbit/s Voice Codecs Main Frame Computer Data Codecs T1/CEPT Interface Digital Line Interface Digital Network Interface Data Codec
Digital Line Interface
256 kbit/s Digital Line
160/80 kbit/s
Main Frame Computer Voice Codec Main Frame Computer Data Codec Digital Network Interface
Voice Codec
Figure 8 - Voice-Data integration using the Data Codec
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ISO-CMOS
Codec converts analog signals into the ST-BUS format while the Data Codec does a similar conversion for low speed data. The information in the ST-BUS format can be switched via the Digital Switch to any of the other interfaces and subsequently transmitted over the appropriate lines to the remote destination. At the remote end, the original signal is regenerated by another codec. The remote equipment can be part of a local area network or it may be accessed through leased T1/ CEPT digital lines. Access to remote equipment via the T1/CEPT leased lines is acquired through the T1/ CEPT interface (MT8976). Full duplex transmission at 1.544 or 2.048 Mbps is possible with this interface. The Digital Network Interface Circuit (DNIC), the MT8972, is capable of providing 160 kbps full duplex transmission over single telephone pair wiring. This device can support two 64 kbps channels, allowing two data codecs to be interfaced to it at the remote end. Simple, low cost data sets can be constructed using the data codec and the DNIC.
MT8950
A simplified interface for transmitting and receiving RS-232 data signals is illustrated in Figure 9. The Codec is selected to receive and transmit low speed data in the NRZ format. The data transmitted by the terminal equipment in the RS-232 format is inverted and level shifted to TTL-compatible levels before being fed into the D X1 input on the Codec. The signal is converted into the ST-BUS format and transmitted via the DSTo output in one channel timeslot when the ST-BUS interface is enabled by F1i and CA, as dictated by the system channel assignment scheme. During this same time period the Codec accepts the 8 bit data arriving on the incoming ST-BUS stream which is output at the STo1 pin on the MT8980. The data is decoded and the original signal input at the remote end is regenerated and output at the DR1 pin. This signal is level shifted, inverted and transmitted to the terminal. The codec in this particular application requires no other programming. Loading of the Control Register via the CSTi input is optional. If this input is tied to ground, the Codec will operate in mode 0 (the normal mode). Note that the SCLK input is tied low. Thus synchronization pulses will not be transmitted and
Digital Switch MT8980 STi3 STi1 STo0 STo1 C4i F0i
AA A AAAAAAAAAAAA AA AAAAAAAAAAAA A AA A AA Timing A AA A AAAAAAAAAAAAAAAAAAA AAAA AA AAAAAAAAAAAAAAACircuitry A AA AAA A AA AAA A MPU AA AAAAAAAAAAAAA AA A AA A AA AAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAA AA AA AA AA AA Channel AA AA AA AA AA AssignmentAA AA AA Circuit AA AA AA AAAA AA AAAAAAAAAAAAAA AAAA AA AAAA AA AAAAAAAAAAAAAAAAAAAAAAAAA AAAA AA AA AA AA Scan Point AA AA AA AA Interface AA AA AAAAAAAAAAA AA AA AAAAAAAAAAAAAAA AA AA AAAA AA
+ 5V MT8950 1 2 3 4 5 6 7 8 CSTi DSTi C2i DSTo F1i CA DF VDD 24
RxE 9 DX 1 10 DX 2 11 NRZo 12 V SS
23 NC 22 PRST 21 NC 20 NC 19 D R1 18 D R2 17 DA 16 SPo 15 SPi 14 DP 13 SCLK
R C
Line Drivers /Receivers TxD FROM DTE RxD RS-232 TTL R = 210 K C = 1.0 F
Figure 9 - Simplified RS-232 Interface using the Data Codec
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MT8950
ISO-CMOS
RTS CTS DSR DTR RLSD TxD RxD DTE RS-232 TTL Digital PBX AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A A A A A A A A MT8950 MT8980 MT8950 A A Receiver Receiver A A A A A A A A A A DX 2 DSTi DSTi DX 2 STo1 STo3 Bipolar to Bipolar to A A A A Unipolar Unipolar A A A A DX 1 DX 1 Converter Converter A A A A A A DSTo DSTo STi1 STi3 A A A A A A DR2 Unipolar Unipolar A A DR2 A A to Bipolar to Bipolar A A A A DR 1 Converter A A Converter DR 1 A A A A A A A A A A Line Driver Line Driver A A A A MPU A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A TTL RS-232 DTE RTS CTS Bipolar RZ signal Line Driver / Receiver NRZ / Bipolar Converter Random Logic or Microcomputer Level Converters DSR DTR RLSD TxD RxD Level Converters Random Logic or Microcomputer NRZ / Bipolar Converter Line Driver / Receiver
Bipolar RZ signal
Figure 10 - Block Diagram Illustration of a Scheme to Submultiplex RS-232 Control Signals the codec cannot be used in the local carrier mode. If this facility is to be used, an appropriate clock can be input to the device. The long SPACE detection circuitry and the Data Activity output can be used for monitoring the codec if necessary. Figure 10 shows a block diagram schematic of a circuit which could be used to submultiplex RS-232 control signals with the data. The data and control signals are operated on by the microprocessor or the logic circuitry and subsequently transmitted as a three level signal. The control signals are encoded as bipolar violations. Since the control status does not change very frequently during a call, this information is transmitted only when no data is available. Circuitry near the Codec converts the bipolar signal into a unipolar format and inputs it at DX1 and DX2. Conversely, the low speed data from the Codec output at D R1 and DR2 is first converted to the bipolar format before being transmitted.The Data Codec is selected to operate in the RZ format.
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The microprocessor or the random logic circuit examines the received signal for violations. If a stream of violations is detected, then the signal is interpreted to be control information. The detected violations are decoded and the appropriate change in the status of the RS-232 control signals is implemented. If no violations are detected then the incoming signal is considered to be the data and it is rerouted to the RxD pin of the RS-232 connector. The microprocessor could also be used in the initial call setup and for error checking of the received control information. This scheme could be used to provide transparent modem capability to any of the ST-BUS based equipment.
ISO-CMOS
Absolute Maximum Ratings*- Voltages are with respect to ground (VSS) unless otherwise stated.
Parameter 1 2 3 4 5 6 7 8 9 Supply Voltage DC Input Voltage DC Output Voltage Input Diode Current ( VI<0 or VI>VDD) Output Diode Current ( VO<0 or VO>VDD ) DC Output Current, per pin DC Supply or Ground Current StorageTemperature Package Power Dissipation (CERDIP) TA= 25o C Symbol VDD VIN VOUT IIK IOK IO IDD/ISS TST -65 Min -0.5 VSS-0.3 VSS-0.3
MT8950
Max 7.0 VDD+0.3 VDD+0.3 10 20 25 50 150 1.0
Units V V V mA mA mA mA
oC
PD * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
W
Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics 1 2 3 Supply Voltage Operating Frequency Operating Temperature Sym VDD fCK TA 0 Min 4.5 Typ 5.0 2.048 70 Max 5.5 Units V MHz
o
Test Conditions
C
Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
DC Electrical Characteristics o o
Characteristics 1 2 S U P Quiescent Supply Current Operating supply current
VDD =5.0V10%; VSS=0V; TA=0 C to 70 C - Voltages are with respect to ground (VSS) unless otherwise stated.
Sym IQS IDD
Min
Typ
Max 150 1.0
Units A mA
Test Conditions All outputs unloaded All inputs @ VSS All outputs unloaded. Input pins 2 and 3 clocked at 2.048 MHz. Pins 1,8,15,20,21 @ VSS Pins 5,6,7,9,10,13 and 22 @VDD
3
TTL inputs1 HIGH voltage LOW voltage I N P U T S CMOS inputs 2 HIGH voltage LOW voltage CMOS Schmitt inputs 3 HIGH voltage LOW voltage SPi Comparator ON Voltage SPi Comparator OFF Voltage
VIH VIL VIH VIL VIH VIL VT+ VT-
2.0 VSS 3.5 VSS 3.0 VSS 2.25 2.0 2.5
VDD 0.8 VDD 1.5 VDD 1.0 2.75
V V V V V V V V VDD = 5V VDD = 5V = 5V
4
5
6 7
8 Input Leakage Current IIN 1 10 A VDD Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing. 1. Include DSTi, CSTi, C2i, F1i and SCLK 2. Include DF 3. Include RxE,D X1, D X 2 and PRST
6-15
MT8950
ISO-CMOS
DC Electrical Characteristics
Characteristics 1 2 3 4 5 6 O U T P U T S Output LOW voltage Output HIGH Voltage
VDD =5.0V10%; VSS=0V; TA=0o C to 70oC - Voltages are with respect to ground (VSS) unless otherwise stated.
Sym VOL VOH IOL IOH IOL IOH
Min
Typ
Max 0.05
Units V V
Test Conditions | IO |< 1.0 A VDD = 5V | IO |< 1.0 A VDD = 5V VOL=0.4V VOH=2.4V VOL=0.4V VOH=2.4V
4.95 2.2 -3.5 8.9 -14.0 2.8 -4.2 11.1 -16.8
Output LOW Current (On all outputs except DSTo) Output HIGH Current (On all outputs except DSTo) Output LOW Current (On DSTo output) Output HIGH Current (On DSTo output)
mA mA mA mA
7 Output Leakage Current IOZ 1 10 A Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics - Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 C2i Clock Frequency C2i Clock Rise Time C2i Clock Fall Time Clock Duty Cycle (C2i & SCLK) SCLK Clock Frequency SCLK Clock Rise Time SCLK Clock Fall Time F1i and CA Rise Time F1i and CA Fall Time F1i and CA Setup Time F1i and CA Hold Time DSTo Rise Time DSTo Fall Time Propagation Delay From Clock (C2i) To Output (DSTo) enable. Propagation Delay From Clock (C2i) To Output (DSTo). Input Rise Time (DSTi, CSTi) Input Fall Time (DSTi, CSTi) DSTi, CSTi Setup Time DSTi, CSTi Hold Time PRST Low Time fSCLK tSCLKR tSCLKF tER tEF tES tEH tOR tOF tPZH tPZL tPLH tPHL tIR tIF tISH tISL tIH 0 90 488 25 -25 25 100 100 125 125 100 100 0 Sym fCK tCR tCF 50 0.6 128 50 50 100 100 Min 2.028 Typ 2.048 Max 2.068 50 50 Units MHz ns ns % kHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note 1 Note 1 Note 1 Note 1 Test Conditions
Timing is over recommended temperature & power supply voltages. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing. Note 1: R L =10K to V DD , C L =150 pF to VSS 6-16
ISO-CMOS
MT8950
125 s C2i INPUT F1i
INTERNAL ENABLE
AAAAAAAA AAAAAAAA AAAAAAAA 7 AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAAA AAAA AAAAAAAA AAAAAAAAA AAAA AAAA 0 AAAAAAAA AAAAAAAAA AAAAAAAA AAAAAAAAA AAAA AAAAAAAA AAAAAAAAA AAAA AAAAAAAA AAAAAAAAA AAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA 7 AAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAAAA
DSTo OUTPUT DSTi/ CSTi INPUTS CA
6
5
4
3
2
1
HIGH IMPEDANCE
6
7
6
5
4
3
2
1
0
7
6
Figure 11 - Timing Diagram - 125 s Frame Period
AA AAAAAAAAAAAAAAAAAAAAAAAAAAAA A 90% C2i 50% Input 10%
tCR F1i, CA Input
tCF 90% 10%
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A tEF
tER tEH
tES AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA DSTo AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA High AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA Output AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA Impedance AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tPLZ tPZH
Figure 12 - Timing Diagram - ST-BUS Interface Enable
AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA 90% 50% 10%
C2i Input
DSTo Output
tCR AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AA 90% 50% 10% tOR
tCF
tPLH AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A 90% DSTi, CSTi 50% Input 10% tIR
tPHL
tOF
tIH tISH
tIF tISL
Figure 13 - Timing Diagram - ST-BUS Input/Output
6-17
MT8950
NOTES:
ISO-CMOS
6-18

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